1. Field of the Invention
The present invention relates to semiconductor chip packages, and more particularly, to multi-chip packages.
2. Description of the Related Arts
Electronic appliances are becoming smaller and lighter as a result of developments in the semiconductor industry and users' demands. One of the technologies for providing compact integrated circuitry for use in such appliances is multi-chip packaging. With multi-chip packaging, multiple semiconductor chips are mounted on a leadframe to form a single package. Multi-chip packaging is often applied to integrated circuits used in cellular telephones where miniaturization and light weight are critical. For these uses, multiple memories, such as Flash memory, synchronous DRAM, etc., are packaged into a single package, such as, a TSOP (thin small outline package). The chips can be enclosed in a single package in two ways, a three-dimensional stack package in which one chip is above another chip and a two-dimensional package in which chips are disposed in or on a horizontal plain. Between the two multi-chip packages, stack packaging is more efficient in minimizing the footprint of the package but is more complicated and has greater difficulty in guaranteeing a definite package thickness.
FIG. 1 is a sectional view of a conventional multi-chip stack package 60. In multi-chip package 60, an adhesive 91 attaches a first chip 61 to a second chip 71, and an adhesive 92 attaches the second chip 71 to a die pad 82 of a leadframe. Active surfaces of chips 61 and 71 face upward. Inner leads 81 of package 60 are disposed around die pad 82, and bonding wires 93 and 94 connect bonding pads 62 and 72 of chips 61 and 71 to corresponding inner leads 81. After the wirebonding that attaches bonding wires 93 and 94, transfer-molding encapsulates chips 61 and 71, die pad 82, inner leads 81 and wires 93 and 94 with a molding compound and forms a package body 95. As shown in FIG. 1, die pad 82 is below the level of inner leads 81. The difference of level between inner leads 81 and die pad 82 is called the "down-set".
Multi-chip package 60 has a structure similar to a conventional plastic package, and thus a large part of conventional plastic packaging technology can be applied to multi-chip package 60. However, stacking multiple chips in a package with a limited thickness may require thinning of a semiconductor wafer after integrated circuit fabrication. A large wafer with an 8 or 12 inch diameter may break during a thinning process such as back-lapping or during handling of the wafer after the thinning. In addition, multi-chip package 60 may require a thin package body 95 above first chip 61 and below die pad 82, and a low height of wire 93 so as to meet package thickness limitation. However, the length of wire 93 may be so long due to the structure of package 60 that controlling the height of wire 93 is difficult. As a result, a poor transfer molding can expose wire 93, first chip 61 or die pad 82. Accordingly, selecting optimal thicknesses for wafers or the package body of package 60 in the conventional multi-chip stack package is difficult. Therefore, a multi-chip stack package structure that provides a wider process window of manufacturing the package is needed.